View ADSP-21367KBPZ-X_3833406.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

a preliminary technical data sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc ? processor adsp-21367 rev. prd information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel #: 781.329.4700 www.analog.com fax #: 781.326.8703 ? 2006 analog devices, inc. all rights reserved. summary high performance 32-bit/40-bit floating point processor optimized for high performance audio processing audio decoder and post proce ssor-algorithm support with 32-bit floating-point implementations non-volatile memory may be configured to support audio decoders and post processor-algorithms like pcm, dolby digital ex, dolby prologic ii x, dolby digital plus, dolby headphone, dts 96/24, neo:6, dts es, dts lossless, mpeg2 aac, mpeg2 2channel, mp3, wmapro, and multi- channel encoder. functions like bass management, delay, speaker equalization, graphic equalization, decoder/post- processor algorithm combin ation support will vary depending upon the chip version and the system configu- rations. please visit www.analog.com single-instruction multiple -data (simd) computational architecture on-chip memory2m bit of on-chip sram and a dedicated 6m bit of on-chip mask-programmable rom code compatible with all othe r members of the sharc family the adsp-21367 is available with a 333 mhz core instruction rate with unique audio centric peripherals such as the digi- tal audio interface, s/pdif transceiver, serial ports, 8-channel asynchronous samp le rate converter, precision clock generators, and more. for complete ordering infor- mation, see ordering guide on page 49 . figure 1. function al block diagram pwm 24 11 32 sdram co n tr o ll e r 3 8 asynchronous mem o ry interface c o n t r o l p i n s address da t a control external port flags 4-15 spi port (2) timers (3) two wire interface uart (2) d p i r o u t i n g u n i t di gi t al per ip h era l i n te r fa c e gp io flags/ irq/timex p 4 serial ports (8) input data port/ pdap d a i r o u t i n g u n i t spdif (rx/tx) digital audio interface iod(32) addr data io a(2 4) 4blocksof on-chip memory 2m bit ram, 6m bit rom pm da ta b u s dm data bus 32 p m a d d re ss bu s dm address bus 64 px re giste r process ing element (p ey) process ing element (p ex) ti mer instruction cache 32-bit 48 -bit dag1 8 4 32 core pro cessor program se quencer dma controller 34 channels s memory-to- memory dma (2) iop re gis te r (me mory mapp ed) control, status, & data buffers jtag test & emulation dag2 8 4 32 i/o processor da i pin s dpi pins 64 32 14 20 src (8 channels) p recis ion clo ck generators (4)
rev. prd | page 2 of 52 | april 2006 adsp-21367 preliminary technical data key features processor core at 333 mhz (3 ns) core instruction rate, the adsp-21367 per- forms 2 gflops/666 mmacs 2m bit on-chip, sram (0.75m bit in blocks 0 and 1, and 0.25m bit in blocks 2 and 3) for simultaneous access by the core processor and dma 6m bit on-chip, mask-programmable, rom (3m bit in block 0 and 3m bit in block 1) dual data address generators (dags) with modulo and bit- reverse addressing zero-overhead looping with single-cycle loop setup, provid- ing efficient program sequencing single instruction multiple data (simd) architecture provides: two computational processing elements concurrent execution code compatibility with othe r sharc family members at the assembly level parallelism in buses and computational units allows: sin- gle cycle executions (with or without simd) of a multiply operation, an alu operation, a dual memory read or write, and an instruction fetch transfers between memory and core at a sustained 6.4g bytes/s bandwidth at 333 mhz core instruction rate input/output features dma controller supports: 34 zero-overhead dma channels for transfers between adsp-21367 internal memory and a variety of peripherals 32-bit dma transfers at peripheral clock speed, in parallel with full-speed processor execution 32-bit wide external port provides glueless connection to both synchronous (sdram) and asynchronous memory devices programmable wait state options: 2 sclk to 31 sclk cycles delay-line dma engine maintains circular buffers in exter- nal memory with tap/offset based reads sdram accesses at 133 mhz and asynchronous accesses at 66 mhz four memory select lines allo ws multiple external memory devices digital audio interface (dai) incl udes eight serial ports, four precision clock generators, an input data port, an s/pdif transceiver, an 8-channel asyn chronous sample rate con- verter, and a signal routing unit digital peripheral interface (dpi) includes three timers, two uarts, two spi ports, and an i 2 c compatible two wire inter- face port (twi) eight dual data line serial ports that operate at up to 50m bits/s on each data line each has a clock, frame sync and two data lines that can be configured as either a receiver or transmitter pair tdm support for telecommunications interfaces including 128 tdm channel support for newer telephony interfaces such as h.100/h.110 up to 16 tdm stream support, each with 128 channels per frame companding selection on a per channel basis in tdm mode input data port, configurable as eight channels of serial data or seven channels of serial data and up to a 20-bit wide parallel data channel signal routing unit provides configurable and flexible con- nections between all dai/dpi components 2 muxed flag/irq lines 1 muxed flag/timer expired line /ms pin 1 muxed flag/irq /ms pin dedicated audio components s/pdif compatible digital audio receiver/transmitter sup- ports eiaj cp-340 (cp-1201), iec-958, aes/ebu standards left-justified, i 2 s, or right-justified serial data input with 16, 18, 20 or 24-bit word widths (transmitter) four independent asynchronous sample rate converters (src). each converter has separate serial input and output ports, a deemphasis filter providing up to -128 db snr per- formance, stereo sample rate converter (src) and supports left-justified, i 2 s, tdm and right-justified modes and 24, 20, 18 and 16 audio data word lengths. pulse width modulation provides: 16 pwm outputs configured as four groups of four outputs supports center-aligned or edge-aligned pwm waveforms rom based security features include: jtag access to memory permitted with a 64-bit key protected memory regions that can be assigned to limit access under program cont rol to sensitive code pll has a wide variety of software and hardware multi- plier/divider ratios dual voltage: 3.3 v i/o, 1.3 v core available in 256-ball sbga and 208-lead mqfp packages (see ordering guide on page 49 )
adsp-21367 preliminary technical data rev. prd | page 3 of 52 | april 2006 table of contents summary ................................................................1 key features processor core .................................2 input/output features ............................................2 dedicated audio components ..................................2 general description ..................................................4 adsp-21367 family core architecture .. .....................4 adsp-21367 memory .............................................5 external memory ...................................................5 adsp-21367 input/output features . ..........................7 system design .......................................................9 development tools .............................................. 10 additional information ......................................... 11 pin function descriptions ........................................ 12 data modes ........................................................ 14 boot modes ........................................................ 14 core instruction rate to clkin ratio modes ............. 14 adsp-21367 specifications ....................................... 15 operating conditions ........................................... 15 electrical characteristics ........................................ 15 package information ............................................ 16 maximum power dissipation ................................. 16 esd sensitivity .................................................... 16 absolute maximum ratings ................................... 16 timing specifications ........................................... 17 output drive currents .......................................... 41 test conditions ................................................... 41 capacitive loading ............................................... 41 thermal characteristics ........................................ 42 256-ball sbga pinout .. ............................................ 43 208-lead mqfp pinout ............................................ 46 package dimensions ................................................ 47 surface mount design .......................................... 48 ordering guide ...................................................... 49 revision history 5/06Crev prd updated ordering guide with x-grade model numbers. see ordering guide on page 49
rev. prd | page 4 of 52 | april 2006 adsp-21367 preliminary technical data general description the adsp-21367 sharc processor is a members of the simd sharc family of dsps that feat ure analog devices' super har- vard architecture. the adsp-21367 is source code compatible with the adsp-2126x and adsp-2 116x dsps as well as with first generation adsp-2106x sharc processors in sisd (single-instruction, single-dat a) mode. the adsp-21367 is a 32-bit/40-bit floating point processors optimized for high per- formance automotive audio applications with its large on-chip sram and mask-programmable rom, multiple internal buses to eliminate i/o bottlenecks, and an innovative digital audio interface (dai). as shown in the functional block diagram on page 1 , the adsp-21367 uses two computationa l units to deliver a signifi- cant performance increase over the previous sharc processors on a range of dsp algorithms. fabricated in a state-of-the-art, high speed, cmos process, th e adsp-21367 processor achieves an instruction cycle time of 3.0 ns at 333 mhz. with its simd computational ha rdware, the adsp-21367 can perform two gflops running at 333 mhz. table 1 shows performance benc hmarks for the adsp-21367. the adsp-21367 continues sharc s industry leading stan- dards of integration for dsps, combining a high performance 32-bit dsp core with integrated, on-chip system features. the block diagram of the adsp-21367 on page 1 , illustrates the following architec tural features: ? two processing elements, each of which comprises an alu, multiplier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer with instruction cache ? pm and dm buses capable of supporting four 32-bit data transfers between me mory and the core at every core pro- cessor cycle ? three programmable interval timers with pwm genera- tion, pwm capture/pulse width measurement, and external event counter capabilities ?on-chip sram (2m bit) ?on-chip mask-progr ammable rom (6m bit) ? jtag test access port the block diagram of the adsp-21367 on page 1 also illustrates the following architectural features: ? dma controller ? eight full duplex serial ports ? digital audio interface that includes four precision clock generators (pcg), an input da ta port (idp), an s/pdif receiver/transmitter, eight ch annels asynchronous sample rate converters, eight serial ports, eight serial interfaces, a 16-bit parallel input port (pdap) , a flexible signal routing unit (dai sru). ? digital peripheral interface that includes three timers, an i 2 c ? -compatible interface, two uarts, two serial periph- eral interfaces (spi), and a flexible signal routing unit (dpi sru). adsp-21367 family core architecture the adsp-21367 is code compatible at the assembly level with the adsp-2126x, adsp-21160, an d adsp-21161, and with the first generation adsp-2106x sharc processors. the adsp-21367 shares architectural features with the adsp-2126x and adsp-2116x simd sharc processors, as detailed in the following sections. simd computational engine the adsp-21367 contains two co mputational processing ele- ments that operate as a single-instruction multiple-data (simd) engine. the processing elements are referred to as pex and pey and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both processing ele- ments, but each processing elem ent operates on different data. this architecture is efficient at executing math intensive dsp algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the pr ocessing elements. because of this requirement, entering simd mode also doubles the band- width between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with each access of memory or the register file. independent, parallel computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform all opera- tions in a single cycl e. the three units within each processing element are arranged in paralle l, maximizing computational throughput. single multifunctio n instructions execute parallel alu and multiplier operations . in simd mode, the parallel table 1. adsp-21367 benchmarks (at 333 mhz) benchmark algorithm speed (at 333 mhz) 1024 point complex fft (radix 4, with reversal) 27.9 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode 1.5 ns iir filter (per biquad) 1 6.0 ns matrix multiply (pipelined) [3x3] [3x1] [4x4] [4x1] 13.5 ns 23.9 ns divide (y/) 10.5 ns inverse square root 16.3 ns
adsp-21367 preliminary technical data rev. prd | page 5 of 52 | april 2006 alu and multiplier operations occur in both processing ele- ments. these computation unit s support ieee 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is contained in each pro- cessing element. the register fi les transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-regist er (16 primary, 16 secondary) register files, combined with the adsp-2136x enhanced har- vard architecture, allow unco nstrained data flow between computation units and internal memory. the registers in pex are referred to as r0Cr15 and in pey as s0Cs15. single-cycle fetch of instruction and four operands the adsp-21367 features an enhanc ed harvard architecture in which the data memory (dm) bu s transfers data and the pro- gram memory (pm) bus transfer s both instructions and data (see figure 1 on page 1 ). with the adsp-21367s separate pro- gram and data memory buses and on-chip instruction cache, the processor can simultaneously fetch four operands (two over each data bus) and one instruct ion (from the cache), all in a single cycle. instruction cache the adsp-21367 includes an on-c hip instructio n cache that enables three-bus operat ion for fetching an instruction and four data values. the cache is select iveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing. data address generators wi th zero-overhead hardware circular buffer support the adsp-21367s two data addr ess generators (dags) are used for indirect addressing an d implementing circular data buffers in hardware. circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags of th e adsp-21367 contain sufficient registers to allow the cr eation of up to 32 circular buff- ers (16 primary register se ts, 16 secondary). the dags automatically handle address pointer wraparound, reduce over- head, increase performance, and simplify implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations, for concise programming. for example, the adsp-21367 can conditionally exec ute a multiply, an add, and a subtract in both processing el ements while branching and fetch- ing up to four 32-bit values from memoryall in a single instruction. adsp-21367 memory the adsp-21367 adds the following architectural features to the simd sharc family core. on-chip memory the adsp-21367 contains two mega bits of inte rnal ram and six megabits of internal mask -programmable rom. each block can be configured for different combinations of code and data storage (see table 2 on page 6 ). each memory block supports single-cycle, independent accesses by the core processor and i/o processor. the adsp-21367 memory architecture, in combina- tion with its separate on-chip buses, allo w two data transfers from the core and one from the i/ o processor, in a single cycle. the adsp-21367s, sram can be configured as a maximum of 64k words of 32-bit data, 128k words of 16-bit data, 42k words of 48-bit instructions (or 40-bit da ta), or combinations of differ- ent word sizes up to two megabits. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit float- ing-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point for- mats is performed in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block st ores data using the dm bus for transfers, and the other block stor es instructions and data using the pm bus for transfers. using the dm bus and pm buses, with one bus dedicated to each memory block, assures si ngle-cycle execution with two data transfers. in this case, the instruction must be available in the cache. external memory the external port on the ad sp-21367 sharc provides a high performance, glueless interface to a wide variety of industry- standard memory devi ces. the 32-bit wide bus may be used to interface to synchronous and/or asynchronous memory devices through the use of its separate internal memory controllers: the first is an sdram controller for connection of industry-stan- dard synchronous dram devices and dimms (dual inline memory module), while the seco nd is an asynchronous mem- ory controller intended to interface to a variety of memory devices. four memory select pins enable up to four separate devices to coexist, supporting any desired combination of syn- chronous and asynchronous device types. nonsdram external memory address space is shown in table 3 . sdram controller the sdram controller provides an interface to up to four sepa- rate banks of industry-standard sdram devices or dimms, at speeds up to f sclk . fully compliant with the sdram standard, each bank can has its own memory select line (ms0 Cms3 ), and can be configured to contain between 16m bytes and 128m bytes of memory. sdram external memory address space is shown in table 4 . the controller maintains all of the banks as a contiguous address space so that the processo r sees this as a single address space, even if different size devices are used in the different banks.
rev. prd | page 6 of 52 | april 2006 adsp-21367 preliminary technical data a set of programmable timing para meters is available to config- ure the sdram banks to support slower memory devices. the memory banks can be configured as either 32 bits wide for max- imum performance and bandwidth or 16 bits wide for minimum device count an d lower system cost. the sdram controller address, data, clock, and command pins can drive loads up to 30 pf. fo r larger memory systems, the sdram controller external buffer timing should be selected and external buffering should be provided so that the load on the sdram controller pins does not exceed 30 pf. asynchronous controller the asynchronous memory contro ller provides a configurable interface for up to four sepa rate banks of memory or i/o devices. each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety of memory devices including sram, rom, flash, and eprom, as well as i/o devices that interface with standard memory con- trol lines. bank 0 occupies a 14. 7m word window and banks 1, 2, and 3 occupy a 16m word window in the processors address space but, if not fully populated, these windows are not made contiguous by the memory contro ller logic. the banks can also be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of interfacing to a range of memories and i/o devices tailored either to high performance or to low cost and power. the asynchronous memory contro ller is capable of a maximum throughput of 267 m bytes/sec using a 66 mhz external bus speed. other features include 8-bi t to 32-bit and 16-bit to 32-bit packing and unpacking, booting from bank select 1, and sup- port for delay line dma. table 2. adsp-21367 internal memory space iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom 0x0004 0000C0x0004 bfff block 0 rom 0x0008 0000C0x0008 ffff block 0 rom 0x0008 0000C0x0009 7fff block 0 rom 0x0010 0000C0x0012 ffff reserved 0x0004 f000C0x0004 ffff reserved 0x0009 4000C0x0009 ffff reserved 0x0009 e0000C0x0009 ffff reserved 0x0013 c000C0x0013 ffff block 0 ram 0x0004 c000C0x0004 efff block 0 ram 0x0009 0000C0x0009 3fff block 0 ram 0x0009 8000C0x0009 dfff block 0 ram 0x0013 0000C0x0013 bfff block 1 rom 0x0005 0000C0x0005 bfff block 1 rom 0x000a 0000C0x000a ffff block 1 rom 0x000a 0000C0x000b 7fff block 1 rom 0x0014 0000C0x0016 ffff reserved 0x0005 f000C0x0005 ffff reserved 0x000b 4000C0x000b ffff reserved 0x000b e000C0x000b ffff reserved 0x0017 c000C0x0017 ffff block 1 ram 0x0005 c000C0x0005 efff block 1 ram 0x000b 0000C0x000b 3fff block 1 ram 0x000b 8000C0x000b dfff block 1 ram 0x0017 0000C0x0017 bfff block 2 ram 0x0006 0000C0x0006 0fff block 2 ram 0x000c 0000C0x000c 1554 block 2 ram 0x000c 0000C0x000c 1fff block 2 ram 0x0018 0000C0x0018 3fff reserved 0x0006 1000C0x0006 ffff reserved 0x000c 1555C0x000d ffff reserved 0x000c 2000C0x000d ffff reserved 0x0018 4000C0x001b ffff block 3 ram 0x0007 0000C0x0007 0fff block 3 ram 0x000e 0000C0x000e 1554 block 3 ram 0x000e 0000C0x000e 1fff block 3 ram 0x001c 0000C0x001c 3fff reserved 0x0007 1000C0x0007 ffff reserved 0x000e 1555C0x000f ffff reserved 0x000e 2000C0x000f ffff reserved 0x001c 4000C0x001f ffff table 3. external memory for non sdram addresses bank size in words address range bank 0 14m 0x0020 0000 C 0x00ff ffff bank 1 16m 0x0400 0000 C 0x04ff ffff bank 2 16m 0x0800 0000 C 0x08ff ffff bank 3 16m 0x0c00 0000 C 0x0cff ffff table 4. external memory for sdram addresses bank size in words address range bank 0 62m 0x0020 0000 C 0x03ff ffff bank 1 64m 0x0400 0000 C 0x07ff ffff bank 2 64m 0x0800 0000 C 0x0bff ffff bank 3 64m 0x0c00 0000 C 0x0fff ffff
adsp-21367 preliminary technical data rev. prd | page 7 of 52 | april 2006 adsp-21367 input/output features the adsp-21367 i/o processor prov ides 34 channels of dma, as well as an extensive set of peripherals. these include a 20 pin digital audio interface which controls: ? eight serial ports ? s/pdif receiver/transmitter ? four precision clock generators ? four stereo sample rate converters ? internal data port/parallel data acquisition port the adsp-21367 processor also contains a 14 pin digital peripheral interface which controls: ? three general-purpose timers ? two serial peripheral interfaces ?two universal asynchrono us receiver/transmitters (uarts) ? a two wire interface/i 2 c dma controller the adsp-21367s on-chip dma co ntroller allows data trans- fers without processor inte rvention. the dma controller operates independently and invi sibly to the processor core, allowing dma operations to oc cur while the core is simulta- neously executing its program in structions. dma transfers can occur between the adsp -21367s internal memory and its serial ports, the spi-compatible (serial peripheral interface) ports, the idp (input data port), the parallel data acquisition port (pdap), or the uart. thirty-four channels of dma are available on the adsp-21367sixteen via the serial ports, eight via the input data port, four for the uarts, tw o for the spi interface, two for the external port, and two for memory-to-memory transfers. programs can be downloaded to the adsp-21367 using dma transfers. other dma features include interrupt generation upon completion of dma transfers, and dma chaining for automatic linked dma transfers. delay line dma the adsp-21367 processor provides delay line dma function- ality. this allows processor reads and writes to external delay line buffers (and hence to external memory) with limited core interaction. digital audio and digital peripheral interfaces (dai/dpi) the digital audio and digital periphal interfaces (dai and dpi) provide the ability to connect va rious peripherals to any of the dsps dai or dpi pins (dai_p20C1 and dpi_p14C1). programs make these connections using the signal routing units (sru1 and sru2), shown in figure 1 . the srus are matrix routing units (or group of multiplexers) that enables the peripherals provided by the dai and dpi to be interconnected under software cont rol. this allows easy use of the associated peripherals for a much wider variety of applica- tions by using a larger set of al gorithms than is possible with non configurable signal paths. the dai and dpi also includes ei ght serial ports, an s/pdif receiver/transmitter, four prec ision clock generators (pcg), eight channels of synchronous sample rate converters, and an input data port (idp). the idp provides an additional input path to the adsp-21367 core, conf igurable as either eight chan- nels of i 2 s serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. each data channel has its own dma channel that is independent from the adsp-21367's serial ports. for complete information on using the dai and dpi, see the adsp-2136x sharc processor ha rdware reference for the adsp-21367/8/9 processors. serial ports the adsp-21367 features eight sy nchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as the analog devices ad183x family of audio codecs , adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial ports are enabled via 16 programmable and simultaneous receive or transmit pins that support up to 32 transmit or 32 receive channels of audio da ta when all eight sports are enabled, or eight full duplex tdm streams of 128 channels per frame. the serial ports operate at a maximum data rate of 50m bits/s. serial port data can be automatically transferred to and from on-chip memory via dedicated dma channels. each of the serial ports can work in conjunct ion with another serial port to provide tdm support. one sport provides two transmit sig- nals while the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in five modes: ? standard dsp serial mode ? multichannel (tdm) mode with support for packed i 2 s mode ?i 2 s mode ?packed i 2 s mode ? left-justified sample pair mode left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/receivedone sample on the high segment of the frame sync, the other on the low segment of the frame sync. programs have control over var- ious attributes of this mode. each of the serial ports supports the left-justified sample pair and i 2 s protocols (i 2 s is an industry standard interface com- monly used by audio codecs, adcs, and dacs such as the analog devices ad183x family), with two data pins, allowing four left-justified sample pair or i 2 s channels (using two stereo devices) per serial port, with a maximum of up to 32 i 2 s chan- nels. the serial ports permit little-endian or big-endian transmission formats an d word lengths selectable from 3 bits to 32 bits. for the left-justified sample pair and i 2 s modes, data-
rev. prd | page 8 of 52 | april 2006 adsp-21367 preliminary technical data word lengths are selectable between 8 bits and 32 bits. serial ports offer selectable synchron ization and transmit modes as well as optional -law or a-law companding selection on a per channel basis. serial port clocks and frame syncs can be inter- nally or extern ally generated. the serial ports also contain fr ame sync error detection logic where the serial ports detect fram e syncs that arrive early (for example frame syncs that arrive while the transmission/recep- tion of the previous word is occurring). all the serial ports also share one dedicated error interrupt. s/pdif compatible digital audio receiver/transmitter and synchronous/asynchronous sample rate converter the s/pdif receiver/transmitter has no separate dma chan- nels. it receives audio data in serial format and converts it into a biphase encoded signal. the serial data input to the receiver/transmitter can be form atted as left justified, i 2 s or right justified with word widt hs of 16, 18, 20, or 24 bits. the serial data, clock, and frame sync inputs to the s/pdif receiver/transmitter are routed th rough the signal routing unit (sru). they can come from a va riety of sources such as the sports, external pins, the precision clock generators (pcgs), or the sample rate converters (src), and are controlled by the sru control registers. the sample rate converter contains four src blocks and is the same core as that used in the ad1896 192 khz stereo asynchro- nous sample rate converter and provides up to 128 db snr. the src block is used to perform synchronous or asynchronous sample rate conversion across independent stereo channels, without using internal processor resources. the four src blocks can also be configured to oper ate together to convert multi- channel audio data without phase mismatches. finally, the src is used to clean up audio data fr om jittery clock sources such as the s/pdif receiver. digital peripheral interface (dpi) the digital peripheral interfac e provides connections to two serial peripheral interface port s (spi), two universal asynchro- nous receiver-transmitters (uarts), a two wire interface (twi), 12 flags, and thre e general-purpose timers. serial peripheral (compatible) interface the adsp-21367 sharc processor co ntains two serial periph- eral interface ports (spis). the spi is an industry standard synchronous serial link, enabling the adsp-21367 spi compati- ble port to communicate with ot her spi compatible devices. the spi consists of two data pins, one device select pin, and one clock pin. it is a full-duplex sy nchronous serial interface, sup- porting both master and slave mo des. the spi port can operate in a multimaster environment by interfacing with up to four other spi compatible devices, eith er acting as a master or slave device. the adsp-21367 spi compat ible peripheral implemen- tation also features programmable baud rate and clock phase and polarities. the adsp-21367 spi compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. uart port the adsp-21367 processor provid es a full-duplex universal asynchronous receiver/transmitter (uart) port, which is fully compatible with pc-standard uarts. the uart port provides a simplified uart interface to other peripherals or hosts, sup- porting full-duplex, dma-supporte d, asynchronous transfers of serial data. the uart also ha s multiprocessor communication capability using 9-bit address detection. this allows it to be used in multidrop networks through the rs-485 data interface stan- dard. the uart port also includes support for 5 data bits to 8 data bits, 1 or 2 stop bits, and none, even, or odd parity. the uart port supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. the uart port's baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk / 1,048,576) to (f sclk /16) bits per second. ? supporting data formats from 7 bits to12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. where the 16-bit uart_divisor comes from the dlh register (most significant 8 bits) and d ll register (least significant 8bits). in conjunction with the general-purpose timer functions, auto- baud detection is supported. timers the adsp-21367 has a total of four timers: a core timer that can generate periodic software interrupts and three general purpose timers that can generate period ic interrupts and be indepen- dently set to operate in one of three modes: ?pulse waveform generation mode ?pulse width co unt/capture mode ? external event watchdog mode the core timer can be configured to use flag3 as a timer expired signal, and each genera l purpose timer has one bidirec- tional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32- bit pulse width register. a sin- gle control and status register enables or disables all three general purpose time rs independently.
adsp-21367 preliminary technical data rev. prd | page 9 of 52 | april 2006 two wire interface port (twi) the twi is a bi-directional 2-wire, serial bus used to move 8-bit data while maintaining compliance with the i 2 c bus protocol. the twi master incorporates the following features: ? simultaneous master and sl ave operation on multiple device systems with support for multi master data arbitration ? digital filtering and timed event processing ? 7-bit and 10-bit addressing ? 100k bits/s and 400k bits/s data rates ? low interrupt rate pulse width modulation the pwm module is a flexible , programmable, pwm waveform generator that can be programmed to generate the required switching patterns for various a pplications related to motor and engine control or audio power control. the pwm generator can generate either center-aligned or edge-align ed pwm wave- forms. in addition, it can gene rate complementary signals on two outputs in paired mode or independent signals in non paired mode (applicable to a single group of four pwm waveforms). the entire pwm module has four groups of four pwm outputs each. therefore, this module generates 16 pwm outputs in total. each pwm group produces two pairs of pwm signals on the four pwm outputs. the pwm generator is capable of operating in two distinct modes while generating center-aligned pwm waveforms: single update mode or double update mode. in single update mode the duty cycle values are programmab le only once per pwm period. this results in pwm patterns that are symmetrical about the mid-point of the pwm period. in double update mode, a sec- ond updating of the pwm regist ers is implemented at the mid- point of the pwm period. in this mode, it is possible to produce asymmetrical pwm patterns that produce lower harmonic dis- tortion in three-ph ase pwm inverters. rom based security the adsp-21367 has a rom securi ty feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. when using this feature, the pr ocessor does not boot-load any external code, executing exclus ively from internal sram/rom. additionally, the processor is no t freely accessible via the jtag port. instead, a unique 64-bit ke y, which must be scanned in through the jtag or test access port will be assigned to each customer. the device will ignore a wrong key. emulation fea- tures and external boot modes are only available after the correct key is scanned. system design the following sections provide an introduction to system design options and power supply issues. program booting the internal memory of the adsp-21367 boots at system power-up from an 8-bit eprom via the external port, an spi master, an spi slave, or an inte rnal boot. booting is determined by the boot configuratio n (bootcfg1C0) pins (see table 7 on page 14 ). selection of the boot source is controlled via the spi as either a master or slave device, or it can immediately begin exe- cuting from rom. power supplies the adsp-21367 has separate powe r supply connections for the internal (v ddint ), external (v ddext ), and analog (a vdd /a vss ) power supplies. the internal and analog supplies must meet the 1.3 v requirement. the external supply must meet the 3.3 v requirement. all external supply pins must be connected to the same power supply. note that the analog supply pin (a vdd ) powers the adsp- 21367s internal clock generator pll. to produce a stable clock, it is recommended that pcb designs use an external filter circuit for the a vdd pin. place the filter components as close as possible to the a vdd /a vss pins. for an example circuit, see figure 2 . (a recommended ferrite chip is the murata blm18ag102sn1d). to reduce noise coupling, the pc b should use a parallel pair of power and ground planes for v ddint and gnd. use wide traces to connect the bypass capacitors to the analog power (a vdd ) and ground (a vss ) pins. note that the a vdd and a vss pins specified in figure 2 are inputs to the processo r and not the analog ground plane on the boardthe a vss pin should connect directly to dig- ital ground (gnd) at the chip. target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test acce ss port of the adsp-21367 pro- cessor to monitor and control the target board processor during emulation. analog devices dsp tools product line of jtag emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and proces- sor stacks. the processor's jtag interface ensures that the emulator will not affect target system loading or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware user's guide. figure 2. analog power (a vdd ) filter circuit hi z ferrite bead chip locate all components close to a vdd and a vss pins a vdd a vss 100nf 10nf 1nf adsp-213xx v ddint
rev. prd | page 10 of 52 | april 2006 adsp-21367 preliminary technical data development tools the adsp-21367 is supported with a complete set of crosscore ? software and hardware development tools, including analog devices emulators and visualdsp++ ? devel- opment environment. the same emulator hardware that supports other sharc processors also fully emulates the adsp-21367. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assembler (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accura te instruction-level simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathematical functions. a key point for these tools is c/c++ code efficiency. the compiler ha s been developed for efficient translation of c/c++ code to dsp assembly. the sharc has architectural features that impr ove the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to non intrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the software developer to passively gather important code executio n metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottlenecks in software quickly and effi- ciently. by using the profiler , the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? trace instruction execution ? perform linear or statistical profiling of program execution ? fill, dump, and graphically plot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ idde lets programmers define and manage dsp software development. its di alog boxes and property pages let programmers configure and manage all of the sharc devel- opment tools, including the colo r syntax highlighting in the visualdsp++ editor. this capability permits programmers to: ? control how the development tools process inputs and generate outputs ? maintain a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unschedule d regions, semaphores, events, and device flags. the vdk also supports priority-based, pre- emptive, cooperative, and time-s liced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but ca n also be used via standard command line tools. when the vdk is used, the development environment assists th e developer with many error-prone tasks and assists in managi ng system resources, automating the gen- eration of various vdk based objects, and visualizing the system state, when debugging an application that uses the vdk. visualdsp++ component softwa re engineering (vcse) is analog devices technology fo r creating, using, and reusing software components (indepen dent modules of substantial functionality) to quickly and reliably assemble software applica- tions. download components from the web and drop them into the application. publish component archives from within visualdsp++. vcse supports co mponent implementation in c/c++ or assembly language. use the expert linker to visually manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical form, easily move code and data to different areas of the processo r or external memory with the drag of the mouse, examine run time stack and heap usage. the expert linker is fully compatible with the existing linker defi- nition file (ldf), a llowing the developer to move between the graphical and textual environments. in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc processor pc plug-in cards. third party software tools include dsp libraries, real-time operating systems, and block diagram design tools.
adsp-21367 preliminary technical data rev. prd | page 11 of 52 | april 2006 designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs in order to test and debug hardware and software systems. analog devices has supplied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. nonintrusive in-circuit emulation is assured by the use of the processors jtag interfacethe emulator do es not affect target system loading or timing. the emulator uses the tap to access the internal features of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the processor must be halted to send data and commands, but once an operation has been completed by the emulator, the dsp system is se t running at full speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. evaluation kit analog devices offers a range of ez-kit lite ? evaluation plat- forms to use as a cost effective method to learn more about developing or prototyping appl ications with analog devices processors, platforms, and softwa re tools. each ez-kit lite includes an evaluation board along with an evaluation suite of the visualdsp++ development and debugging environment with the c/c++ compiler, assemble r, and linker. also included are sample applicat ion programs, power supply, and a usb cable. all evaluation versions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-kit lite board connects the board to the usb port of the users pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on -board flash device to store user-specific boot code, enabling the board to run as a standal- one unit without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software fo r the ez-kit lite or any cus- tom defined system. connecting one of analog devices jtag emulators to the ez-kit lite board enables high-speed, non- intrusive emulation. additional information this data sheet provides a ge neral overview of the adsp-21367 architecture and functionality. for detailed information on the adsp-2136x family core architecture and instruction set, refer to the adsp-2136x sharc processo r hardware reference for the adsp-21367/8/9 processors and the adsp-2136x sharc processor programming reference .
rev. prd | page 12 of 52 | april 2006 adsp-21367 preliminary technical data pin function descriptions the following symbols appear in the type column of table 5 : a = asynchronous, g = ground, i = input, o = output, p = power supply, s = synchron ous, (a/d) = active drive, (o/d) = open drain, and t = three-state, (pd) = pull-down resistor, (pu) = pull-up resistor. table 5. pin list name type state during /after reset description addr 23C0 o/t (pu) pulled high/driven low external address. the adsp-21367 outputs addresses for external memory and peripherals on these pins. data 31C0 i/o (pu) pulled high/pulled high external data. data pins can be multiplexed to support external memory interface data (i/o), the pdap (i), flags (i/o), and pwm (o). after reset, all data pins are in emif mode and flag(0-3) pins are in flags mode (default). when configured using the idp_pdap_ctl register, idp channel 0 scans the data 31C8 pins for parallel input data. dai _p 20C1 i/o with program- mable pu 1 pulled high/ pulled high digital audio interface pins . these pins provide the physical interface to the dai sru. the dai sru configuration registers define the combination of on-chip audio centric peripheral inputs or outputs connected to the pin, and to the pins output enable. the configuration registers then determines the exact behavior of the pin. any input or output signal present in the dai sru may be routed to any of these pins. the dai sru provides the connection from the serial po rts (8), the src module, the pwm module, the s/pdif module, input data ports (2), and the precision clock generators (4), to the dai_p20C1 pins. pull-ups can be disabl ed via the dai_pin_pullup register. dpi _p 14C1 i/o with program- mable pu 1 pulled high/ pulled high digital peripheral interface. these pins provide the physical interface to the dpi sru. the dpi sru configuration registers define th e combination of on-chip peripheral inputs or outputs connected to the pin and to th e pins output enable. the configuration registers of these peripherals then determines the exact behavior of the pin. any input or output signal present in the dpi sru may be routed to any of these pins. the dpi sru provides the connection from the timers (3), spis (2), uarts (2), flags (12) twi (1), and general-purpose i/o (9) to the dpi_p14C1 pins. the twi output is an open-drain outputso the pins used for i 2 c data and clock should be connected to logic level 0. pull-ups can be disabled via the dpi_pin_pullup register. ack i (pu) memory acknowledge. external devices can deassert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory controllers, or other peripherals to hold off completion of an external memory access. rd o/t (pu) pulled high/ driven high external port read enable. rd is asserted whenever the adsp-21367 reads a word from external memory. wr o/t (pu) pulled high/ driven high external port write enable. wr is asserted when the adsp-21367 writes a word to external memory. sdras o/t (pu) pulled high/ driven high sdram row address strobe. connect to sdrams ras pin. in conjunction with other sdram command pins, defines the oper ation for the sdram to perform. sdcas o/t (pu) pulled high/ driven high sdram column address select. connect to sdram's cas pin. in conjunction with other sdram command pins, defines the operation for the sdram to perform. sdwe o/t (pu) pulled high/ driven high sdram write enable. connect to sdrams we or w buffer pin.
adsp-21367 preliminary technical data rev. prd | page 13 of 52 | april 2006 sdcke o/t (pu) pulled high/ driven high sdram clock enable. connect to sdrams cke pin. enables and disables the clk signal. for details, see the data sh eet supplied with the sdram device. sda10 o/t (pu) pulled high/ driven low sdram a10 pin. enables applications to refresh an sdram in parallel with non- sdram accesses. this pin replaces the ds ps a10 pin only during sdram accesses. sdclk0 o/t high-z/driving sdram clock output 0. ms 0C1 o/t (pu) pulled high/ driven high memory select lines 0C1. these lines are asserted (low) as chip selects for the corre- sponding banks of external memory. the ms 3-0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memory access is occurring, the ms 3-0 lines are inactive; they are active, however, when a condi- tional memory access instruction is executed, whether or not the condition is true. the ms1 pin can be used in eport/flash boot mode. see the hardware reference for more information. flag[0]/irq0 i/o high-z/high-z flag0/interrupt request0. flag[1]/irq1 i/o high-z/high-z flag1/interrupt request1. flag[2]/irq2 / ms2 i/o with program- mable pu (for ms mode) high-z/high-z flag2/interrupt requ est/memory select2. flag[3]/timexp/ ms3 i/o with program- mable pu (for ms mode) high-z/high-z flag3/timer expired/memory select3. tdi i (pu) test data input (jtag). provides serial data for the boundary scan logic. tdo o/t test data output (jtag). serial scan output of the boundary scan path. tms i (pu) test mode select (jtag). used to control the test state machine. tck i test clock (jtag). provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up, or held low for proper operation of the adsp-21367. trst i (pu) test reset (jtag). resets the test state machine. trst must be assert ed (pulsed low) after power-up or held low for proper operation of the adsp-21367. emu o/t (pu) emulation status. must be connected to the adsp-21367 analog devices dsp tools product line of jtag emulator target board connectors only. clk_cfg 1C0 i core/clkin ratio control. these pins set the start up clock frequency. see table 8 for a description of the clock configuration modes. note that the operating freq uency can be changed by prog ramming the pll multiplier and divider in the pmctl register at any time after the core comes out of reset. boot_cfg 1C0 i boot configuration select. these pins select the boot mode for the processor. the bootcfg pins must be valid before reset is asserted. see table 7 for a description of the boot modes. reset i processor reset. resets the adsp-21367 to a known state. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock . after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power-up. table 5. pin list name type state during /after reset description
rev. prd | page 14 of 52 | april 2006 adsp-21367 preliminary technical data data modes the upper 32 data pins of the external memory interface are muxed (using bits in the sysctl register) to support the exter- nal memory interface data (input/output), the pdap (input only), the flags (input/output), and the pwm channels (out- put). table 6 provides the pin settings. boot modes core instruction rate to clkin ratio modes for details on processor timing, see timing specifications and figure 4 on page 17 . xtal o crystal oscillator terminal. used in conjunc tion with clkin to drive an ex ternal cr ystal. clkin i local clock in. used with xtal. clkin is the processors clock input. it configures the adsp-21367 to use either its internal clock generator or an external clock source. con- necting the necessary components to clki n and xtal enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the adsp-21367 to use an external clock such as an external clock oscillator. clkin may not be halted, changed, or operated below the specified frequency. clkout o/t driven low/ driven high local clock out. clkout can also be configured as a reset out pin.the functionality can be switched between the pll output cloc k and reset out by se tting bit 12 of the pmctreg register. the default is reset out. 1 pull-up can be enabled/disabled, valu e of pull-up cannot be programmed. table 5. pin list name type state during /after reset description table 6. function of data pins data pin mode data31C16 data15C8 data7C0 000 epdata32C0 001 flags/pwm15C0 1 epdata15C0 010 flags/pwm15C0 1 flags15C8 epdata7C0 011 flags/pwm15C0 1 flags15C0 100 pdap (data + ctrl) epdata7C0 101 pdap (data + ctrl) flags7C0 110 reserved 111 three-state all pins 1 these signals can be flags or pwm or a mix of both. however, they can be selected only in groups of four. their function is det ermined by the control signals flags/pwm_sel. for more information, see the adsp-2136x sharc processor hardware refe rence for the adsp-21367/8/9 processors . table 7. boot mode selection bootcfg1C0 booting mode 00 spi slave boot 01 spi master boot 10 eprom/flash boot table 8. core instruction rate/ clkin ratio selection clkcfg1C0 core to clkin ratio 00 6:1 01 32:1 10 16:1
adsp-21367 preliminary technical data rev. prd | page 15 of 52 | april 2006 adsp-21367 specifications operating conditions electrical characteristics parameter 1 1 specifications subject to change without notice. min max unit v ddint internal (core) supply voltage 1.235 1.365 v a vdd analog (pll) supply voltage 1.235 1.365 v v ddext external (i/o) supply voltage 3.13 3.47 v v ih 2 2 applies to input and bidirec tional pins: ack, data31C0, flag3C0, da i_px, dpi_px, bootcfgx, clkcfgx, reset , tck, tms, tdi, trst . high level input voltage @ v ddext = max 2.0 v ddext + 0.5 v v il 2 low level input voltage @ v ddext = min C0.5 +0.8 v v ih _ clkin 3 3 applies to input pin clkin. high level input voltage @ v ddext = max 1.74 v ddext + 0.5 v v il _ clkin low level input voltage @ v ddext = min C0.5 +1.19 v parameter 1 test conditions min typ max unit v oh 2 high level output voltage @ v ddext = min, i oh = C1.0 ma 3 2.4 v v ol 2 low level output voltage @ v ddext = min, i ol = 1.0 ma 3 0.4 v i ih 4, 5 high level input current @ v ddext = max, v in = v ddext max 10 a i il 4 low level input current @ v ddext = max, v in = 0 v 10 a i ilpu 5 low level input current pull-up @ v ddext = max, v in = 0 v 200 a i ozh 6, 7 three-state leakage current @ v ddext = max, v in = v ddext max 10 a i ozl 6 three-state leakage current @ v ddext = max, v in = 0 v 10 a i ozlpu 7 three-state leakage current pull-up @ v ddext = max, v in = 0 v 200 a i dd - intyp 8, 9 supply current (internal) t cclk = 3.0 ns, v ddint = 1.3 900 ma ai dd 10 supply current (analog) a vdd = max 10 ma c in 11, 12 input capacitance f in =1 mhz, t case =25c, v in =1.3 v 4.7 pf 1 specifications subject to change without notice. 2 applies to output and bidirection al pins: addr23-0, data31-0, rd , wr , flag3C0, dai_px, dpi_px, sdras , sdcas , sdwe , sdcke, sda10, sdclk0, ms 0-1, emu , tdo, clkout. 3 see output drive currents on page 41 for typical drive current capabilities. 4 applies to input pins: bootcfgx, clkcfgx, tck, reset , clkin. 5 applies to input pins with internal pull-ups: ack, trst , tms, tdi. 6 applies to three-statable pins without pull- ups and those with pull-ups disabled: flag3 :0, dai_px (pull-ups disabled), dpi_px ( pull-ups disabled), sdclk0, and tdo. 7 applies to three-statable pins with pull-ups: addr23-0, data31-0, rd , wr , dai_px, dpi_px, sdras , sdcas , sdwe , sdcke, sda10, ms 0-1, emu . 8 typical internal current data reflec ts nominal operating conditions. 9 see engineer-to-engineer note (no. tbd) for further information. 10 characterized, but not tested. 11 applies to all signal pins. 12 guaranteed, but not tested.
rev. prd | page 16 of 52 | april 2006 adsp-21367 preliminary technical data package information the information presented in figure 3 provide details about the package branding for the ad sp-21367 processor. for a com- plete listing of prod uct availability, see ordering guide on page 49 . maximum power dissipation see engineer-to-engineer note (ee-tbd) for detailed thermal and power information regarding maximum power dissipation. for information on package thermal specifications, see thermal characteristics on page 42 . absolute maximum ratings stresses greater than those listed in table 10 may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd sensitivity figure 3. typical package brand table 9. package brand information brand key field description t temperature range pp package type z lead free option (optional) ccc see ordering guide vvvvvv.x assembly lot code n.n silicon revision yyww date code vvvvvv.x n.n tppzccc s adsp-2136x a yyww country_of_origin table 10. absolute maximum ratings parameter rating internal (core) supply voltage (v ddint )C0.3 v to +1.5 v analog (pll) supply voltage (a vdd )C0.3 v to +1.5 v external (i/o) supply voltage (v ddext )C0.3 v to +4.6 v input voltage C0.5 v to v ddext +0.5 v output voltage swing C0.5 v to v ddext +0.5 v load capacitance 200 pf storage temperature range C65 c to +150 c junction temperature under bias 125 c caution esd (electrostatic discharge) sensitive device. el ectrostatic charges as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge without detection. although the adsp-21367 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid perfor mance degradation or loss of functionality.
adsp-21367 preliminary technical data rev. prd | page 17 of 52 | april 2006 timing specifications the adsp-21367s internal clock (a multiple of clkin) pro- vides the clock signal for timi ng internal memory, processor core, and serial ports. during reset, program the ratio between the processors internal clock frequency and external (clkin) clock frequency with the clkcfg1C0 pins (see table 8 on page 14 ). to determine switching frequencies for the serial ports, divide down the internal clock, using the programmable divider control of each port (divx for the serial ports). the adsp-21367s internal clock sw itches at higher frequencies than the system input clock (clk in). to generate the internal clock, the processor uses an in ternal phase-locked loop (pll). this pll-based clocking minimi zes the skew between the sys- tem clock (clkin) signal and th e processors internal clock. figure 4 shows core to clkin ratios of 6:1, 16:1, and 32:1 with external oscillator or cr ystal. note that more ratios are possible and can be set through software using the power management control register (pmctl). for more information, see the adsp- 2136x sharc processor programming reference . note the definitions of vari ous clock periods shown in table 12 which are a function of clkin and the appropriate ratio con- trol shown in table 11 . use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 36 on page 41 under test conditions for voltage refer- ence levels. switching characteristics specify how the processor changes its signals. circuitry external to th e processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. figure 4. core clock and system clock relationship to clkin pllm clkin cclk (core clock) plliclk xtal xtal osc clkout clk-cfg [1:0] (6:1, 16:1, 32:1) pclk (peripheral clock) indiv 1, 2 diven 2,4,8,16 sdclk (sdram clock) table 11. adsp-21367 clkout and cclk clock generation operation timing requirements description calculation clkin input clock 1/t ck cclk core clock 1/t cclk table 12. clock periods timing requirements description 1 1 where: sr = serial port-to-core clock ratio (wide range, determined by sport clkdiv bits in divx register) spir = spi-to-core clock ratio (wide ra nge, determined by spibaud register setting) spiclk = spi clock sdr = sdram-to-core clock ratio (values de termined by bit 20 to bit 18 of the pmctl register) t ck clkin clock period t cclk (processor) core clock period t pclk (peripheral) clock period = 2 t cclk t sclk serial port clock period = (t pclk ) sr t sdclk sdram clock period = (t cclk ) sdr t spiclk spi clock period = (t pclk ) spir
rev. prd | page 18 of 52 | april 2006 adsp-21367 preliminary technical data power-up sequencing the timing requirements for pr ocessor startup are given in table 13 . table 13. power up sequencing timing requirements (processor startup) parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext C50 +200 ms t clkvdd 1 clkin valid after v ddint /v ddext valid 0 +200 ms t clkrst clkin valid before reset deasserted 10 2 s t pllrst pll control setup before reset deasserted 20 s switching characteristic t corerst core reset deasserted after reset deasserted 4096t ck + 2 t cclk 3, 4 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their 1.3 volt rails an d 3.3 volt rails. voltage ramp rates can vary from micro seconds to hundreds of milliseconds depending on the desi gn of the power supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case start-up timing of crystal oscillators. refer to your crystal oscillato r manufacturers data sheet for start-up time. assume a 25 ms maximum oscillator start-up ti me if using the xtal pin and internal osci llator circuit in conjunction with an ex ternal crystal. 3 applies after the power-up sequence is complete. subseque nt resets require a minimum of 4 clkin cycles for reset to be held low in order to properly initialize and propagate default states at all i/o pins. 4 the 4096 cycle count depends on t srst specification in table 15 . if setup time is not met, 1 additional clkin cycle may be added to the core reset time, resulting in 4097 cycles maximum. figure 5. power-up sequencing clkin reset t rstvdd rstout v ddext v ddint t pllrst t clkrst t clkvdd t ivddevdd clk_cfg1-0 t corerst
adsp-21367 preliminary technical data rev. prd | page 19 of 52 | april 2006 clock input clock signals the adsp-21367 can use an external clock or a crystal. see the clkin pin description in table 5 . the programmer can config- ure the adsp-21367 to use its internal clock generator by connecting the necessary comp onents to clkin and xtal. figure 7 shows the component connec tions used for a crystal operating in fundamental mode. note that the clock rate is achieved using a 16.67 mhz crysta l and a pll multiplier ratio 16:1 (cclk:clkin achieves a clock speed of 333 mhz). to achieve the full core clock rate, programs need to configure the multiplier bits in the pmctl register. table 14. clock input parameter 333 mhz unit min max timing requirements t ck clkin period 18 1 1 applies only for clkcfg1C0 = 00 and defaul t values for pll control bits in pmctl. 100 2 2 applies only for clkcfg1C0 = 10 and defaul t values for pll control bits in pmctl. ns t ckl clkin width low 8 1 45 2 ns t ckh clkin width high 8 1 45 2 ns t ckrf clkin rise/fall (0.4 v to 2.0 v) 3 ns t cclk 3 3 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . cclk period 3.0 1 10 ns t ckj 4, 5 4 actual input jitter should be combined with ac specifications for acc urate timing analysis. 5 jitter specification is maximum peak-to -peak time interval error (tie) jitter. clkin jitter tolerance C250 +250 ps figure 6. clock input clkin t ck t ckh t ckl figure 7. 333 mhz operation (fundamental mode crystal) c1 22pf y1 r1 1m (typical) xtal clkin c2 22pf 24.576mhz r2 47 (typical) adsp-2136x r2 should be chosen to li mi t crystal drive power.
rev. prd | page 20 of 52 | april 2006 adsp-21367 preliminary technical data reset interrupts the following timing specification applies to the flag0, flag1, and flag2 pins when they are config ured as irq0 , irq1 , and irq2 interrupts. table 15. reset parameter min max unit timing requirements t wrst 1 reset pulse width low 4t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequence is comp lete. at power-up, the processors internal ph ase-locked loop requires no more than 1 00 s while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). figure 8. reset clkin reset t wrst t srst table 16. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t pclk +2 ns figure 9. interrupts dai_p20-1 dpi_14-1 flag2-0 (irq2-0) t ipw
adsp-21367 preliminary technical data rev. prd | page 21 of 52 | april 2006 core timer the following timing specification applies to flag3 when it is configured as the core timer (ctimer). timer pwm_out cycle timing the following timing specification applies to timer0, timer1, and timer2 in pwm_out (pulse width modulation) mode. timer signals are routed to the dpi_p14C1 pins through the sru. therefore, the timing specifications provided below are valid at the dpi_p14C1 pins. table 17. core timer parameter min max unit switching characteristic t wctim ctimer pulse width 4 t pclk C 1 ns figure 10. core timer flag3 (ctimer) t wctim table 18. timer pwm_out timing parameter min max unit switching characteristic t pwmo timer pulse width output 2 t pclk C 1 2 (2 31 C 1) t pclk ns figure 11. timer pwm_out timing dpi14-1 (timer2-0) t pwmo
rev. prd | page 22 of 52 | april 2006 adsp-21367 preliminary technical data timer wdth_cap timing the following timing specification applies to timer0, timer1, and timer2 in wdth_cap (pul se width count and capture) mode. timer signals are routed to the dpi_p14C1 pins through the sru. therefore, the timing specification provided below are valid at the dpi_p14C1 pins. pin to pin direct routing (dai and dpi) for direct pin connections only (for example dai_pb01_i to dai_pb02_o). table 19. timer width capture timing parameter min max unit timing requirement t pwi timer pulse width 2 t pclk 2 (2 31 C 1) t pclk ns figure 12. timer width capture timing dpi_14-1 (timer2-0) t pwi table 20. dai pin to pin routing parameter min max unit timing requirement t dpio delay dai/dpi pin input valid to dai output valid 1.5 10 ns figure 13. dai pin to pin direct routing dai_pn dpi_pn t dpio da i_pm dpi_pm
adsp-21367 preliminary technical data rev. prd | page 23 of 52 | april 2006 precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins. for the other ca ses, where the pcgs inputs and outputs are not directly routed to/from dai pins (via pin buffers) there is no timing data available. all timing param- eters and switching characteristics apply to external dai pins (dai_p01 C dai_p20). table 21. precision clock generator (direct pin routing) parameter min max unit timing requirement s t pcgip input clock period 24 ns t strig pcg trigger setup before falling edge of pcg input clock 4.5 ns t htrig pcg trigger hold after falling edge of pcg input clock 3ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 10 ns t dtrigclk pcg output clock delay after pcg trigger 2.5 + ((2.5 + d) t pcgip ) 10 + ((2.5 + d) t pcgip )ns t dtrigfs pcg frame sync delay after pcg trigger 2.5 + ((2.5 + d C ph) t pcgip ) 10 + ((2.5 + d C ph) t pcgip )ns t pcgow output clock period 2 t pcgip 1 C 1 ns d = fsxdiv, ph = fsxphase. for more information, see the adsp-2136x sharc processor hardware reference for the adsp-21367/8/9 processors , precision clock generators chapter. 1 in normal mode. figure 14. precision clock generator (direct pin routing) dai_pn dpi_pn pcg_trigx_i t strig dai_pm dpi_pm pcg_extx_i (clkin) dai_py dpi_py pcg_clkx_o dai_pz dpi_pz pcg_fsx_o t htrig t dpcgio t dtrigfs t pcgip t pcgow t dtrigclk t dpcgio
rev. prd | page 24 of 52 | april 2006 adsp-21367 preliminary technical data flags the timing specifications provided below apply to the flag3C0 and dpi_p14C1 pins, and the serial peripheral interface (spi). see table 5 for more information on flag use. table 22. flags parameter min max unit timing requirement t fipw flag3C0 in pulse width 2 t pclk + 3 ns switching characteristic t fopw flag3C0 out pulse width 2 t pclk C 1.5 ns figure 15. flags dpi_p14-1 (flag3-0 in ) (data31-0) t fipw dpi_p14-1 (flag3-0 out ) (data31-0) t fopw
adsp-21367 preliminary technical data rev. prd | page 25 of 52 | april 2006 sdram interface timing (133 mhz sdclk) table 23. sdram interface timing 1 1 for f cclk = 333 mhz (sdclk ratio = 1:2.5). parameter min max unit timing requirement t ssdat data setup before sdclk 0.58 ns t hsdat data hold after sdclk 1.23 ns switching characteristic t sclk sdclk period 7.5 ns t sclkh sdclk width high 3.65 ns t sclkl sdclk width low 3.65 ns t dcad command, addr, data delay after sdclk 2 2 command pins include: sdcas , sdras , sdwe , msx , sda10, sdcke. 4.8 ns t hcad command, addr, data hold after sdclk 2 1.5 ns t dsdat data disable after sdclk 5.3 ns t ensdat data enable after sdclk 1.6 ns figure 16. sdram interface timing t hcad t hcad t dsdat t ssdat t dcad t ensdat t hsdat t sclkl t sclkh t sclk sdclk data (in) data(out) cmnd addr (out) t dcad
rev. prd | page 26 of 52 | april 2006 adsp-21367 preliminary technical data memory readbus master use these specifications for asyn chronous interfacing to memo- ries. these specifications appl y when the adsp-21367 is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and strobe timing parameters only apply to asynchronous access mode. table 24. memory readbus master parameter min max unit timing requirements t dad address, selects delay to data valid 1, 2 w+t sdclk C5.12 ns t drld rd low to data valid 1 wC 2.9 ns t sds data setup to rd high 2.2 ns t hdrh data hold from rd high 3, 4 0ns t daak ack delay from address, selects 2, 5 t sdclk C9.5+ w ns t dsak ack delay from rd low 4 wC 7.0 ns switching characteristics t drha address selects hold after rd high rh + 0.38 ns t darl address selects to rd low 2 t sdclk C3.3 ns t rw rd pulsewidth w C 1.1 ns t rwr rd high to wr , rd , low hi +t sdclk C 0.8 ns w = (number of wait states specified in amictlx register) t sdclk . hi =rhc + ic (rhc = (number of read hold cycles specified in amictlx register) t sdclk ic = (number of idle cycles sp ecified in amictlx register) t sdclk ). h = (number of hold cycles spec ified in amictlx register) t sdclk . 1 data delay/setup: system must meet t dad , t drld , or t sds. 2 the falling edge of ms x, is referenced. 3 note that timing for ack, data, rd , wr , and strobe timing parameters only apply to asynchronous access mode. 4 data hold: user must meet t hda or t hdrh in asynchronous access mode. see test conditions on page 41 for the calculation of hold time s given capacitive and dc loads. 5 ack delay/setup: user must meet t daak , or t dsak , for deassertion of ack (low). for asynchron ous assertion of ack (high) user must meet t daak or t dsak . figure 17. memory readbus master ack data t darl t rw t dad t daak t hdrh t rwr t drld t drha t dsak t sds address msx rd wr
adsp-21367 preliminary technical data rev. prd | page 27 of 52 | april 2006 memory write bus master use these specifications for asyn chronous interfacing to memo- ries. these specifications appl y when the adsp-21367 is the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and strobe timing parameters on ly apply to asynchronous access mode. table 25. memory writebus master parameter min max unit timing requirements t daak ack delay from address, selects 1, 2 t sdclk C 9.7 + w ns t dsak ack delay from wr low 1, 3 w C 4.9 ns switching characteristics t dawh address, selects to wr deasserted 2 t sdclk C3.1+ w ns t dawl address, selects to wr low 2 t sdclk C2.7 ns t ww wr pulsewidth w C 0.8 ns t ddwh data setup before wr high t sdclk C3.0+ w ns t dwha address hold after wr deasserted h + 0.15 ns t dwhd data hold after wr deasserted h + 0.02 ns t wwr wr high to wr , rd low t sdclk C1.5+ h ns t ddwr data disable before rd low 2t sdclk C 4.11 ns t wde wr low to data enabled t sdclk C 3.5 ns w = (number of wait states specified in amictlx register) t sdclk . h = (number of hold cycles specified in amictlx register) t sdclk . 1 ack delay/setup: system must meet t daak , or t dsak , for deassertion of ack (low). for asynchronous as sertion of ack (high) user must meet t daak or t dsak . 2 the falling edge of msx is referenced. 3 note that timing for ack, data, rd , wr , and strobe timing parameters only applies to asynchronous access mode. figure 18. memory writebus master ack data t dawl t ww t daak t wwr t wde t ddwr t dwha t dawh t dsak t ddwh t dwhd address msx wr rd
rev. prd | page 28 of 52 | april 2006 adsp-21367 preliminary technical data serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. serial port signals (sclk, fs, data channel a, data channel b) are routed to the dai_p20C1 pins using the sru. therefore, the timing specifications provided below are valid at the dai_p20C1 pins. table 26. serial portsexternal clock parameter min max unit timing requirements t sfse 1 fs setup before sclk (externally generated fs in either transmit or receive mode) 2.5 ns t hfse 1 fs hold after sclk (externally generated fs in either transmit or receive mode) 2.5 ns t sdre 1 receive data setup before receive sclk 2.5 ns t hdre 1 receive data hold after sclk 2.5 ns t sclkw sclk width 10 ns t sclk sclk period 20 ns switching characteristics t dfse 2 fs delay after sclk (internally generated fs in either transmit or receive mode) 9.5 ns t hofse 2 fs hold after sclk (internally generated fs in either transmit or receive mode) 2 ns t ddte 2 transmit data delay after transmit sclk 9.6 ns t hdte 2 transmit data hold after transmit sclk 2 ns 1 referenced to sample edge. 2 referenced to drive edge. table 27. serial portsinternal clock parameter min max unit timing requirements t sfsi 1 fs setup before sclk (externally generated fs in either transmit or receive mode) 7 ns t hfsi 1 fs hold after sclk (externally generated fs in either transmit or receive mode) 2.5 ns t sdri 1 receive data setup before sclk 7 ns t hdri 1 receive data hold after sclk 2.5 ns switching characteristics t dfsi 2 fs delay after sclk (internally generated fs in transmit mode) 4 ns t hofsi 2 fs hold after sclk (internally gene rated fs in transmit mode) C1.0 ns t dfsi 2 fs delay after sclk (internally generated fs in receive mode) 9 ns t hofsi 2 fs hold after sclk (internally generated fs in receive mode) C1.0 ns t ddti 2 transmit data delay after sclk 3 ns t hdti 2 transmit data hold after sclk C1.0 ns t sclkiw 3 transmit or receive sclk width 2 t pclk C 1.5 2 t pclk ns 1 referenced to the sample edge. 2 referenced to drive edge. 3 minimum sport divisor register value.
adsp-21367 preliminary technical data rev. prd | page 29 of 52 | april 2006 table 28. serial portsenable and three-state parameter min max unit switching characteristics t ddten 1 data enable from external transmit sclk 2 ns t ddtte 1 data disable from external transmit sclk 10 ns t ddtin 1 data enable from internal transmit sclk C1 ns 1 referenced to drive edge. table 29. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse 1 data delay from late external tran smit fs or external receive fs with mce = 1, mfd = 0 7.75 ns t ddtenfs 1 data enable for mce = 1, mfd = 0 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justifi ed sample pair as well as dsp serial mode, and mce = 1, mfd = 0. figure 19. external late frame sync 1 1 this figure reflects change s made to support left-jus tified sample pair mode. drive sample drive dai_p20-1 (sclk) dai_p20-1 (fs) dai_p20-1 (data channel a/b) drive sample drive late external transmit fs external receive fs with mce = 1, mfd = 0 1st bit 2nd bit dai_p20-1 (sclk) dai_p20-1 (fs) 1st bit 2nd bit t hfse/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i t sfse/i t ddte/i t ddtenfs t ddtlfse t hdte/i dai_p20-1 (data channel a/b) note: serial port signals (sclk, fs, data channel a/b ) are routed to the dai_p20-1 pins using the sru. the timing specifications provided here are valid at the dai_p20-1 pins. t hfse/i
rev. prd | page 30 of 52 | april 2006 adsp-21367 preliminary technical data figure 20. serial ports dai_p20-1 (sclk) dai_p20-1 (fs) drive edge sample edge data receive? internal clock data receive ? e x ternal clock drive edge sample edge note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t sdri t hdri t sfsi t hfsi t dfsi t hofsi t sclkiw t sdre t hdre t sfse t hfse t dfse t sclkw t hofse dai_p20-1 (data channel a/b) t ddti drive edge sample edge data transmit ? internal clock t sfsi t hfsi t dfsi t hofsi t sclkiw t hdti note: either the rising edge or falling edge of sclk (external), sclk (internal) can be used as the active sampling edge. t ddte drive edge sample edge data transmit ? external clock t sfse t hfse t dfse t hofse t sclkw t hdte dai_p20-1 (sclk) dai_p20-1 (fs) dai_p20-1 (data channel a/b) dai_p20-1 (sclk) dai_p20-1 (fs) dai_p20-1 (data channel a/b) dai_p20-1 (sclk) dai_p20-1 (fs) dai_p20-1 (data channel a/b) drive edge dai_p20-1 sclk (int) drive edge drive edge sclk dai_p20-1 sclk (ext) t ddtte t ddten t ddtin dai_p20-1 (data channel a/b) dai_p20-1 (data channel a/b)
adsp-21367 preliminary technical data rev. prd | page 31 of 52 | april 2006 input data port the timing requirements for the idp are given in table 30 . idp signals (sclk, fs, sdata) are routed to the dai_p20C1 pins using the sru. therefore, the timing specifications pro- vided below are valid at the dai_p20C1 pins. table 30. idp parameter min max unit timing requirements t sisfs 1 fs setup before sclk rising edge 3.8 ns t sihfs 1 fs hold after sclk rising edge 2.5 ns t sisd 1 sdata setup before sclk rising edge 2.5 ns t sihd 1 sdata hold after sclk rising edge 2.5 ns t idpclkw clock width 9 ns t idpclk clock period 24 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcg's input can be either clkin or any of the dai pins. figure 21. idp master timing dai_p20-1 (sclk) dai_p20-1 (fs) sample edge t sisfs t sihfs t idpclk dai_p20-1 (sdata) t idpclkw t sisd t sihd
rev. prd | page 32 of 52 | april 2006 adsp-21367 preliminary technical data parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table 31 . pdap is the parallel mode operation of channel 0 of the idp. for details on the oper ation of the idp, see the idp chapter of the adsp-2136x sharc pr ocessor hardware reference for the adsp -21367/8/9 processors . note that the most significant 16 bits of external pdap data can be provided through the data31C16 pins. the remaining 4 bits can only be sourced through dai_p4C1. the timing below is valid at the data31C16 pins. table 31. parallel data acquisition port (pdap) parameter min max unit timing requirements t spclken 1 pdap_clken setup before pdap_clk sample edge 2.5 ns t hpclken 1 pdap_clken hold after pdap_clk sample edge 2.5 ns t pdsd 1 pdap_dat setup before sclk pdap_clk sample edge 3.85 ns t pdhd 1 pdap_dat hold after sclk pdap_clk sample edge 2.5 ns t pdclkw clock width 7.0 ns t pdclk clock period 24 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t pclk + 3 ns t pdstrb pdap strobe pulse width 2 t pclk C 1 ns 1 source pins of data are addr7C0, data7C0, or dai pins. source pin s for sclk and fs are: 1) dai pins, 2) clkin through pcg, or 3) dai pins through pcg. figure 22. pdap timing dai_p20-1 (pdap_clk) sample edge t pdsd t pdhd t spclken t hpclken t pdclkw data dai_p20-1 (pdap_clken) t pdstrb t pdhldd dai_p20-1 (pdap_strobe) t pdclk
adsp-21367 preliminary technical data rev. prd | page 33 of 52 | april 2006 pulse width modulation generators sample rate converterserial input port the src input signals (sclk, fs , and sdata) are routed from the dai_p20C1 pins using the sru. therefore, the timing spec- ifications provided in table 33 are valid at the dai_p20C1 pins. table 32. pwm timing parameter min max unit switching characteristics t pwmw pwm output pulse width t pclk C 2 (2 16 C 2) t pclk C 2 ns t pwmp pwm output period 2 t pclk C 1.5 (2 16 C 1) t pclk C 1.5 ns figure 23. pwm timing pwm outputs t pwmw t pwmp table 33. src, serial input port parameter min max unit timing requirements t srcsfs 1 fs setup before sclk rising edge 4 ns t srchfs 1 fs hold after sclk rising edge 5.5 ns t srcsd 1 sdata setup before sclk rising edge 4 ns t srchd 1 sdata hold after sclk rising edge 5.5 ns t srcclkw clock width 9 ns t srcclk clock period 24 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 24. src serial input port timing dai_p20-1 (sclk) dai_p20-1 (fs) sample edge t srcsfs t srchfs t srcclk dai_p20-1 (sdata) t srcclkw t srcsd t srchd
rev. prd | page 34 of 52 | april 2006 adsp-21367 preliminary technical data sample rate converterserial output port for the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to sclk on the output port. the serial data output, sdata, has a hold time and delay specification with regard to sclk. note that sclk rising edge is the sampling edge and the falling edge is the drive edge. table 34. src, serial output port parameter min max unit timing requirements t srcsfs 1 fs setup before sclk rising edge 4 ns t srchfs 1 fs hold before sclk rising edge 5.5 ns t srcclkw clock width 9 ns t srcclk clock period 24 ns switching characteristics t srctdd 1 transmit data delay after sclk falling edge 8.9 ns t srctdh 1 transmit data hold after sclk falling edge 1 ns 1 sdata, sclk, fs can come from any of the dai pins. sclk and fs can also come via pcg or sports . pcg's input can be either clki n or any of the dai pins. figure 25. src serial output port timing dai_p20-1 (sclk) dai_p20-1 (fs) t srcsfs t srchfs dai_p20-1 (sdata) t srctdd t srctdh sample edge t srcclk t srcclkw
adsp-21367 preliminary technical data rev. prd | page 35 of 52 | april 2006 spdif transmitter serial data input to the spdif transmitter can be formatted as left justified, i 2 s or right justified with wo rd widths of 16, 18, 20, or 24 bits. the following sect ions provide timing for the transmitter. spdif transmitterserial input waveforms figure 26 shows the right-justified mode. lrclk is hi for the left channel and lo for the right channel. data is valid on the rising edge of sclk. the msb is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output mode) from an lrclk transition, so that when there are 64 sclk periods per lrclk period, the lsb of the data will be right-justified to the next lrclk transition. figure 27 shows the default i 2 s-justified mode. lrclk is lo for the left channel and hi for the right channel. data is valid on the rising edge of sclk. the msb is left-justified to an lrclk transition but with a single sclk period delay. figure 28 shows the left-justified mode . lrclk is hi for the left channel and lo for the right channel. data is valid on the rising edge of sclk. the msb is left-jus tified to an lrclk transition with no msb delay. figure 26. right-justified mode dai _ p2 0 -1 lrclk dai_p20-1 sclk dai_p20-1 sdata left channel right channel msb-1 msb-2 lsb+2 lsb+1 lsb msb msb-1 msb-2 lsb+2 lsb+1 lsb lsb msb figure 27. i 2 s-justified mode msb-1 msb-2 lsb+2 lsb+1 lsb left channel right channel msb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb dai_p20-1 lrclk dai_p20-1 sclk dai_p20-1 sdata figure 28. left-justified mode left channel right channel msb-1 msb-2 lsb+2 lsb+1 lsb msb msb-1 msb-2 lsb+2 lsb+1 lsb msb msb+1 msb dai_p20-1 lrclk dai_p20-1 sclk dai_p20-1 sdata
rev. prd | page 36 of 52 | april 2006 adsp-21367 preliminary technical data spdif transmitter input data timing the timing requirements for the input port are given in table 35 . input signals (sclk, fs, sdata) are routed to the dai_p20C1 pins using the sru. therefore, the timing specifica- tions provided below are valid at the dai_p20C1 pins. over sampling clock (txclk) switching characteristics the spdif transmitter has an over sampling clock. this txclk input is divided down to generate the biphase clock. table 35. spdif transmitter input data timing parameter min max unit timing requirements t sifs 1 fs setup before sclk rising edge 3 ns t sihfs 1 fs hold after sclk rising edge 3 ns t sisd 1 sdata setup before sclk rising edge 3 ns t sihd 1 sdata hold after sclk rising edge 3 ns t sitxclkw transmit clock width 9 ns t sitxclk transmit clock period 20 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcg's input can be either clkin or any of the dai pins. figure 29. spdif transmitter input timing dai_p20-1 (sclk) dai_p20-1 (fs) sample edge t sisd t sisfs t sisclkw dai_p20-1 (sdata) dai_p20-1 (txclk) t sihd t sihfs t sitxclkw t sitxclk table 36. over sampling clock (txclk) switching characteristics parameter min max unit txclk frequency for txclk = 768 fs 147.5 mhz txclk frequency for txclk = 512 fs 98.4 mhz txclk frequency for txclk = 384 fs 73.8 mhz txclk frequency for txclk = 256 fs 49.2 mhz frame rate 192.0 khz
adsp-21367 preliminary technical data rev. prd | page 37 of 52 | april 2006 spdif receiver the following section describes timing as it relates to the spdif receiver. internal digital pll mode in the internal digital phase-lock ed loop mode the internal pll (digital pll) generates the 512 fs clock. table 37. spdif receiver internal digital pll mode timing parameter min max unit switching characteristics t dfsi lrclk delay after sclk 5 ns t hofsi lrclk hold after sclk C2 ns t ddti transmit data delay after sclk 5 ns t hdti transmit data hold after sclk C2 ns t sclkiw 1 transmit sclk width 38 ns 1 sclk frequency is 64 fs where fs = the frequency of lrclk. figure 30. spdif receiver internal digital pll mode timing drive edge sample edge dai_p20-1 (sclk) dai_p20-1 (fs) dai_p20-1 (data channel a/b) t sclkiw t dfsi t ddti t hofsi t hdti
rev. prd | page 38 of 52 | april 2006 adsp-21367 preliminary technical data spi interfacemaster the adsp-21367 contains two spi ports. the prim ary has dedi- cated pins and the secondary is available through the dpi. the timing provided in table 38 and table 39 applies to both. table 38. spi interface protocol master switching and timing specifications parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input set-up time) 8 ns t hspidm spiclk last sampling edge to data input not valid 2 ns switching characteristics t spiclkm serial clock cycle 8 t pclk C 1.5 ns t spichm serial clock high period 4 t pclk C 1.5 ns t spiclm serial clock low period 4 t pclk C 1.5 ns t ddspidm spiclk edge to data out vali d (data out delay time) 2.5 ns t hdspidm spiclk edge to data out not valid (data out hold time) 2 ns t sdscim flag3C0in (spi device select) low to first spiclk edge 4 t pclk C 2 ns t hdsm last spiclk edge to flag3C0in high 4 t pclk C 2 ns t spitdm sequential transfer delay 4 t pclk C 1 ns figure 31. spi master timing lsb valid msb valid t sspidm t hspidm t hdspidm lsb msb t hspidm t ddspidm mosi (output) miso (input) flag3-0 (output) spiclk (cp = 0) (output) spiclk (cp = 1) (output) t spichm t spiclm t spiclm t spiclkm t spichm t hdsm t spitdm t hdspidm lsb valid lsb msb msb valid t hspidm t ddspidm mosi (output) miso (input) t sspidm cphase = 1 t sdscim cphase = 0 t sspidm
adsp-21367 preliminary technical data rev. prd | page 39 of 52 | april 2006 spi interfaceslave table 39. spi interface protocol slave switching and timing specifications parameter min max unit timing requirements t spiclks serial clock cycle 4 t pclk C 2 ns t spichs serial clock high period 2 t pclk C 2 ns t spicls serial clock low period 2 t pclk C 2 ns t sdsco spids assertion to first spiclk edge cphase = 0 cphase = 1 2 t pclk 2 t pclk ns ns t hds last spiclk edge to spids not asserted, cphase = 0 2 t pclk ns t sspids data input valid to spiclk edge (data input set-up time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase = 0) 2 t pclk ns switching characteristics t dsoe spids assertion to data out active 0 6.8 ns t dsdhi spids deassertion to data high impedance 0 6.8 ns t ddspids spiclk edge to data out valid (data out delay time) 9.4 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t pclk ns t dsov spids assertion to data out valid (cphase = 0) 5 t pclk ns figure 32. spi slave timing t hspids t ddspids t dsdhi lsb msb msb valid t dsoe t ddspids t hdspids miso (output) mosi (input) t sspids spids (input) spiclk (cp = 0) (input) spiclk (cp = 1) (input) t sdsco t spichs t spicls t spicls t spiclks t hds t spichs t sspids t hspids t dsdhi lsb valid msb msb valid t dsoe t ddspids miso (output) mosi (input) t sspids lsb valid lsb cphase = 1 cphase = 0 t sdppw t dsov t hdspids
rev. prd | page 40 of 52 | april 2006 adsp-21367 preliminary technical data jtag test access port and emulation table 40. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys 1 system inputs setup before tck high 7 ns t hsys 1 system inputs hold after tck high 18 ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 7 ns t dsys 2 system outputs delay after tck low t ck 2 + 7 ns 1 system inputs = ad15C0, spids , clkcfg1C0, reset , bootcfg1C0, miso, mosi, spiclk, dai_px, flag3C0. 2 system outputs = miso, mosi, spiclk, dai_px, ad15C0, rd , wr , flag3C0, clkout, emu . figure 33. ieee 1149.1 jtag test access port tck tms tdi tdo system inputs system outputs t stap t tck t htap t dtdo t ssys t hsys t dsys
adsp-21367 preliminary technical data rev. prd | page 41 of 52 | april 2006 output drive currents figure 34 shows typical i-v characteri stics for the output driv- ers of the adsp-21367. the curves represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear table 15 on page 20 through table 40 on page 40 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the sharc apply for the voltage reference levels in figure 35 . timing is measured on signals wh en they cross the 1.5 v level as described in figure 36 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads: 30 pf on all pins (see figure 35 ). figure 39 shows graphically how output delays and holds vary with load capacitance. the graphs of figure 37 , figure 38 , and figure 39 may not be linear outside the ranges shown for typi cal output delay vs. load capac- itance and typical output rise time (20% to 80%, v = min) vs. load capacitance. figure 34. adsp-21367 typical drive figure 35. equivalent device loading for ac measurements (includes all fixtures) figure 36. voltage reference levels for ac measurements sweep (v ddext ) voltage (v) - 20 03.5 0.5 1.0 1.5 2.0 2.5 3.0 0 - 40 - 30 20 40 - 10 s o u r c e ( v d d e x t ) c u r r e n t ( m a ) v ol 3.11v, 125 c 3.3v, 25 c 3.47v, - 45 c v oh 30 10 3.11v, 125 c 3.3v, 25 c 3.47v, - 45 c 1.5v 30pf to output pin 50 input or output 1.5v 1.5v figure 37. typical output rise/fall time (20% to 80%, v ddext = max) figure 38. typical output rise/fall time (20% to 80%, v ddext = min) load capacitance (pf) 8 0 0 100 250 12 4 2 10 6 r i s e a n d f a l l t i m e s ( n s ) 200 150 50 fall y = 0.0467x + 1.6323 y = 0.045x + 1.524 rise load capacitance (pf) 12 0 50 100 150 200 250 10 8 6 4 r i s e a n d f a l l t i m e s ( n s ) 2 0 rise fall y = 0.049x + 1.5105 y = 0.0482x + 1.4604
rev. prd | page 42 of 52 | april 2006 adsp-21367 preliminary technical data thermal characteristics the adsp-21367 processor is rate d for performance over the temperature range specified in operating conditions on page 15 . table 41 and table 42 airflow measurements comply with jedec standards jesd51-2 and jesd51-6 and the junction-to- board measurement complies with jesd51-8. test board design complies with jedec standard s jesd51-9 (sbga). the junc- tion-to-case measurement comp lies with mil- std-883. all measurements use a 2s2p jedec test board. to determine the junction temperature of the device while on the application pcb, use: where: t j = junction temperature ( c) t t = case temperature ( c) measured at the top center of the package jt = junction-to-top (of package) characterization parameter is the typical value from table 41 and table 42 . p d = power dissipation (see ee note no. ee-277 for more information). values of ja are provided for package comparison and pcb design considerations. ja can be used for a first order approxi- mation of t j by the equation: where: t a = ambient temperature c values of jc are provided for pack age comparison and pcb design considerations when an external heatsink is required. values of jb are provided for pack age comparison and pcb design considerations. note that the thermal characteristics val- ues provided in table 41 and table 42 are modeled values. figure 39. typical output delay or hold vs. load capacitance (at ambient temperature) load capacitance (pf) 0 200 50 100 150 10 8 o u t p u t d e l a y o r h o l d ( n s ) -4 6 0 4 2 -2 y = 0.0488x - 1.5923 t j t t jt p d () + = t j t a ja p d () + = table 41. thermal characteristics for 256 ball sbga (no thermal vias in pcb) parameter condition typical unit ja airflow = 0 m/s 12.5 c/w jma airflow = 1 m/s 10.6 c/w jma airflow = 2 m/s 9.9 c/w jc 0.7 c/w jb 5.3 c/w jt airflow = 0 m/s 0.3 c/w jmt airflow = 1 m/s 0.3 c/w jmt airflow = 2 m/s 0.3 c/w table 42. thermal characte ristics for 208-lead mqfp parameter condition typical unit ja airflow = 0 m/s 25.0 c/w jma airflow = 1 m/s 22.5 c/w jma airflow = 2 m/s 21.6 c/w jc 9.6 c/w jt airflow = 0 m/s 0.7 c/w jmt airflow = 1 m/s 0.8 c/w jmt airflow = 2 m/s 0.9 c/w
adsp-21367 preliminary technical data rev. prd | page 43 of 52 | april 2006 256-ball sbga pinout table 43. 256-ball sbga pin assignme nt (numerically by ball number) ball no. signal ball no. signal ball no. signal ball no. signal a01 nc b01 dai5 c01 dai9 d01 dai10 a02 tdi b02 nc c02 dai7 d02 dai6 a03 tms b03 trst c03 gnd d03 gnd a04 clk_cfg0 b04 tck c04 v ddext d04 v ddext a05 clk_cfg1 b05 bootcfg_0 c05 gnd d05 gnd a06 emu b06 bootcfg_1 c06 gnd d06 v ddext a07 dai4 b07 tdo c07 v ddint d07 v ddint a08 dai1 b08 dai3 c08 gnd d08 gnd a09 dpi14 b09 dai2 c09 gnd d09 v ddext a10 dpi12 b10 dpi13 c10 v ddint d10 v ddint a11 dpi10 b11 dpi11 c11 gnd d11 gnd a12 dpi9 b12 dpi8 c12 gnd d12 v ddext a13 dpi7 b13 dpi5 c13 v ddint d13 v ddint a14 dpi6 b14 dpi4 c14 gnd d14 gnd a15 dpi3 b15 dpi1 c15 gnd d15 v ddext a16 dpi2 b16 reset c16 v ddint d16 gnd a17 clkout b17 data30 c17 v ddint d17 v ddext a18 data31 b18 data29 c18 v ddint d18 gnd a19 nc b19 data28 c19 data27 d19 data26 a20 nc b20 nc c20 nc d20 data24 e01 dai11 f01 dai14 g01 dai15 h01 dai17 e02 dai8 f02 dai12 g02 dai13 h02 dai16 e03 v ddint f03 gnd g03 gnd h03 v ddint e04 v ddint f04 gnd g04 v ddext h04 v ddint e17 gnd f17 v ddext g17 v ddint h17 v ddext e18 gnd f18 gnd g18 v ddint h18 gnd e19 data25 f19 gnd g19 data22 h19 data19 e20 data23 f20 data21 g20 data20 h20 data18 j01dai19 k01flag0 l01flag2 m01ack j02 dai18 k02 dai20 l02 flag1 m02 flag3 j03gnd k03gnd l03v ddint m03 gnd j04gnd k04v ddext l04 v ddint m04 gnd
rev. prd | page 44 of 52 | april 2006 adsp-21367 preliminary technical data j17gnd k17v ddint l17 v ddint m17 v ddext j18gnd k18v ddint l18 v ddint m18 gnd j19gnd k19gnd l19data15 m19data12 j20 data17 k20 data16 l20 data14 m20 data13 n01 rd p01 sda10 r01 sdwe t01 sdcke n02 sdclk0 p02 wr r02 sdras t02 sdcas n03 gnd p03 v ddint r03 gnd t03 gnd n04 v ddext p04 v ddint r04 gnd t04 v ddext n17 gnd p17 v ddint r17 v ddext t17 gnd n18 gnd p18 v ddint r18 gnd t18 gnd n19 data11 p19 data8 r19 data6 t19 data5 n20 data10 p20 data9 r20 data7 t20 data4 u01 ms0 v01 addr22 w01 gnd y01 gnd u02 ms1 v02 addr23 w02 addr21 y02 nc u03 v ddint v03 v ddint w03 addr19 y03 nc u04 gnd v04 gnd w04 addr20 y04 addr18 u05 v ddext v05 gnd w05 addr17 y05 nc u06 gnd v06 gnd w06 addr16 y06 nc u07 v ddext v07 gnd w07 addr15 y07 xtal2 u08 v ddint v08 v ddint w08 addr14 y08 clkin u09 v ddext v09 gnd w09 a vdd y09 nc u10 gnd v10 gnd w10 a vss y10 nc u11 v ddext v11 gnd w11 addr13 y11 nc u12 v ddint v12 v ddint w12 addr12 y12 nc u13 v ddext v13 v ddext w13 addr10 y13 addr11 u14 v ddext v14 gnd w14 addr8 y14 addr9 u15 v ddint v15 v ddint w15 addr5 y15 addr7 u16 v ddext v16 gnd w16 addr4 y16 addr6 u17 v ddint v17 gnd w17 addr1 y17 addr3 u18 v ddint v18 gnd w18 addr2 y18 gnd u19 data0 v19 data1 w19 addr0 y19 gnd u20 data2 v20 data3 w20 nc y20 nc table 43. 256-ball sbga pin assignment (n umerically by ball number) (continued) ball no. signal ball no. signal ball no. signal ball no. signal
adsp-21367 preliminary technical data rev. prd | page 45 of 52 | april 2006 figure 40 shows the top view of the sbga ball configuration. figure 41 shows the bottom view of the sbga ball configuration. figure 40. 256-ball sbga ball configuration (bottom view) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t no connect v ddint i/o signals gnd key v ddext a vss a vdd bottom view figure 41. 256-ball sbga ball configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t no connect v ddint i/o signals gnd key v ddext a vss a vdd top view
rev. prd | page 46 of 52 | april 2006 adsp-21367 preliminary technical data 208-lead mqfp pinout table 44. 208-lead mqfp pin assignment (numerically by lead number) pin no. signal pin no. signal pin no. signal pin no. signal 1 vdd 53 vdd 105 vdd 157 vdd 2 data28 54 gnd 106 gnd 158 vdd 3 data27 55 iovdd 107 iovdd 159 gnd 4 gnd 56 addr0 108 sdcas 160 vdd 5 iovdd 57 addr2 109 sdras 161 vdd 6 data26 58 addr1 110 sdcke 162 vdd 7 data25 59 addr4 111 sdwe 163 tdi 8data24 60addr3 112wr 164 trst 9 data23 61 addr5 113 sda10 165 tck 10 gnd 62 gnd 114 gnd 166 gnd 11 vdd 63 vdd 115 iovdd 167 vdd 12 data22 64 gnd 116 sdclk0 168 tms 13 data21 65 iovdd 117 gnd 169 clk_cfg0 14 data20 66 addr6 118 vdd 170 bootcfg0 15 iovdd 67 addr7 119 rd 171 clk_cfg1 16 gnd 68 addr8 120 ack 172 emu 17 data19 69 addr9 121 flag3 173 bootcfg1 18 data18 70 addr10 122 flag2 174 tdo 19 vdd 71 gnd 123 flag1 175 dai4 20 gnd 72 vdd 124 flag0 176 dai2 21 data17 73 gnd 125 dai20 177 dai3 22 vdd 74 iovdd 126 gnd 178 dai1 23 gnd 75 addr11 127 vdd 179 iovdd 24 vdd 76 addr12 128 gnd 180 gnd 25 gnd 77 addr13 129 iovdd 181 vdd 26 data16 78 gnd 130 dai19 182 gnd 27 data15 79 vdd 131 dai18 183 dpi14 28 data14 80 avss 132 dai17 184 dpi13 29 data13 81 avdd 133 dai16 185 dpi12 30 data12 82 gnd 134 dai15 186 dpi11 31 iovdd 83 clkin 135 dai14 187 dpi10 32 gnd 84 xtal2 136 dai13 188 dpi9 33 vdd 85 iovdd 137 dai12 189 dpi8 34 gnd 86 gnd 138 vdd 190 dpi7 35 data11 87 vdd 139 iovdd 191 iovdd 36 data10 88 addr14 140 gnd 192 gnd 37 data9 89 gnd 141 vdd 193 vdd 38 data8 90 iovdd 142 gnd 194 gnd 39 data7 91 addr15 143 dai11 195 dpi6 40 data6 92 addr16 144 dai10 196 dpi5 41 iovdd 93 addr17 145 dai8 197 dpi4 42 gnd 94 addr18 146 dai9 198 dpi3 43 vdd 95 gnd 147 dai6 199 dpi1 44 data4 96 iovdd 148 dai7 200 dpi2
adsp-21367 preliminary technical data rev. prd | page 47 of 52 | april 2006 package dimensions figure 42 shows the package dimensions of the 256-ball sbga and figure 43 the dimensions of the 208-lead mqfp. all dimensions are in millimeters. 45 data5 97 addr19 149 dai5 201 clkout 46 data2 98 addr20 150 iovdd 202 reset 47 data3 99 addr21 151 gnd 203 iovdd 48 data0 100 addr23 152 vdd 204 gnd 49 data1 101 addr22 153 gnd 205 data30 50 iovdd 102 ms1 154 vdd 206 data31 51 gnd 103 ms0 155 gnd 207 data29 52 vdd 104 vdd 156 vdd 208 vdd table 44. 208-lead mqfp pin assignment (num erically by lead number) (continued) pin no. signal pin no. signal pin no. signal pin no. signal figure 42. 256-ball sbga, thermally enhanced (bp-256) 1.27 nom 1.70 max 0.90 0.75 0.60 ball diameter top view a1 ball indicator dimensions are in millimeters and comply with jedec standard mo-192-bal-2. 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 17 19 20 18 r p n m l k j h g f e d c b a y w v u t bottom view 27.00 bsc sq 24.13 ref sq a1 corner index area 0.70 0.60 0.50 1.00 0.80 0.60 0.10 min seating plane 0.20 coplanarity 0.25 min 4x
rev. prd | page 48 of 52 | april 2006 adsp-21367 preliminary technical data surface mount design table 45 is provided as an aide to pcb design. for industry- standard design recommendations, refer to ipc-7351, generic requirements for surface mount design and land pattern standard . figure 43. 208-lea d mqfp (s-208-2) 0.20 0.09 3.60 3.40 3.20 0.50 0.25 0.08 max (lead coplanarity) view a rotated 90 ccw 1 208 157 156 105 104 53 52 top view (pins down) 0.50 bsc 28.20 28.00 sq 27.80 0.27 0.17 (lead pitch) (lead width) seating plane 4.10 max 0.75 0.60 0.45 notes: 1.theactualpositionofeachleadiswithin0.08fromitsideal position when measured in the lateral direction. 2. center dimensions are typical unless otherwise noted. 3. dimensions are in millimeters and comply with jedec standard ms-029, fa-1. 30.85 30.60 sq 30.35 view a pin 1 indicator table 45. bga data for use with surface mount design package ball attach type solder mask opening ball pad size 256-lead ball grid array bga (bp-256) solder mask defined (smd) 0.63 mm 0.73 mm
adsp-21367 preliminary technical data rev. prd | page 49 of 52 | april 2006 ordering guide analog devices offers a wide va riety of audio algorithms and combinations to run on th e adsp-21367 processor. these products are sold as part of a chip set, bundled with necessary application software under special part numbers. for a complete list, visit our web site at www.analog.com/sharc . these product also may contain third party ips that may require users to have authorization from the respective ip holders to receive them. royalty for use of the 3rd party ips may also be payable by users. part number temperature range 1 instruction rate on-chip sram rom operating voltage internal/external package description package option adsp-21367ksz-x 2 0 c to +70 c 266 mhz 2m bit 6m bit 1.2 v/3.3 v 208-lead mqfp s-208-2 adsp-21367kbp-x 0 c to +70 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 ADSP-21367KBPZ-X 2 0 c to +70 c 333 mhz 2m bit 6m bit 1.3 v/3.3 v 256-ball sbga bp-256 1 referenced temperature is ambient temperature. 2 z = pb-free part.
rev. prd | page 50 of 52 | april 2006 adsp-21367 preliminary technical data
adsp-21367 preliminary technical data rev. prd | page 51 of 52 | april 2006
rev. prd | page 52 of 52 | april 2006 adsp-21367 preliminary technical data ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr05267-0-04/06(prd)

▲Up To Search▲

Price & Availability of ADSP-21367KBPZ-X

	To Download ADSP-21367KBPZ-X Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .